1. Field of the Invention
The present invention relates to the design and operation of a serial peripheral interface (SPI) bus having a single master device and multiple slave devices.
2. Background of the Related Art
A serial peripheral interface (SPI) bus is a synchronous serial data link standard that operates in full duplex mode. SPI is sometimes referred to as a “four wire” serial bus, including (1) a clock (CLK) output from a master device to an input on a slave device, (2) a master output, slave input (MOSI), (3) a master input, slave output (MISO), and (4) a slave select (SS) output from the master device. FIG. 1 is a diagram of an SPI bus between a single master device and a single slave device. Typically, both the master and slave devices have a shift register connected in a ring by the MOSI and MISO lines. Data is shifted until the contents of the registers have been exchanged. Each device may then take the data from its register for processing, such as storage into memory. This process may repeat as necessary to transmit any desired data or command.
In some applications, such as a serial general purpose input/output (SGPIO) bus, two or more slave devices are connected in a daisy chain configuration. FIG. 2 is a diagram of an SPI bus between a single master device and three slave devices in a daisy chain. Accordingly, the MOSI pin of the master device is coupled to the MOSI pin of the first slave device, MISO pin of the first slave is coupled to the MOSI pin of the second slave, the MISO pin of the second slave is coupled to the MOSI pin of the third slave, and the MISO pin of the third slave is then coupled to the MISO pin of the master device. In operation, data shifts from one device to the next in the daisy chain such that the master device can provide data or commands to any of the three slave devices, and any/all of the three slave devices can provide data to the master device.
Independent slaves may be implemented if the master device has an independent slave select line for each slave device with which it will communicate. In FIG. 3, the master device has three independent slave select output pins, SS1, SS2 and SS3, that are coupled to the slave select input pins of first, second and third slaves, respectively. Each of the independent slave devices is coupled in parallel with the CLK, MOSI, and MISO lines of the master device, but only the slave device receiving a slave select signal will drive its MISO pin. Other unselected slave devices will simply ignore or disregard the CLK and MOSI signals.